The invention relates to a method of manufacturing a semiconductor device and more particularly, to the semiconductor device manufacturing method using a multilayer resist.
In the immersion exposure process mainly used after the 45 nm node process, dust generation from a wafer edge portion induces exposure failure and lens contamination of an exposure device, and generates a defect in an integrated circuit formed on a wafer, hence to deteriorate the manufacturing yield, which is an obvious problem (FIG. 12).
Therefore, at an immersion exposure time, in order to secure water repellency in a wafer edge portion, it is necessary to correctly apply a top coat material and a resist having the water repellency to the wafer surface including the wafer edge portion. Further, the water repelling processing such as HMDS processing (Hexamethyldisilazane) is required for the wafer surface that is a semiconductor substrate.
Further, according to the miniaturization, in order to suppress reflection from a semiconductor substrate, there is introduced the multilayer resist process such as a process of Bottom Anti Reflection Coating (BARC) that is an anti-reflection film and a coating typed process of Carbon Hard Mask (C-HM) including a silicon (Si)-containing intermediate layer having a function of both anti-reflection and etching resistance and a carbon based underlayer (FIG. 13).
In order to restrain dust generation from the wafer edge portions (particularly, bevel portions) of these organic films, dust elimination according to edge rinse, back rinse, and bevel rinse with various types of solvents at an application time of these organic films and elimination of the residues in the wafer edge portions caused by bevel etching and bevel polishing are considered, as the processing for the edge portion of the organic film.
In the bevel etching and the bevel polishing, however, there are fears such as film exfoliation at a time of forming a barrier metal film after substrate exposure, dust generation caused by an abnormal discharge at a time of forming an interlayer insulating film, and liquid leakage at a time of immersion exposure caused by substrate scart of the bevel portion.
Further, there remain many problems such as elimination property of the organic films and controllability of a cut surface in the edge portion, also in the edge rinse, back rinse, and bevel rinse with various types of solvents (FIG. 14).
As the background technique of this technical field, there is a technique, for example, as disclosed in Japanese Unexamined Patent Application Publication No. 2008-277748. This Patent Application Publication discloses a technique for HMDS processing just after the formation of a target film.
Further, Japanese Patent Application Publication No. 4897056 discloses a technique for water repelling processing by dropping a water repellent chemical liquid from a nozzle of an application device.
In the Proc. of SPIE, Vol. 7274, “Control and reduction of immersion defectivity for yield enhancement at high volume production” (72741P, written by Nakano, 2009), there are considered the optimization of the condition for the HMDS processing to be processed on a substrate, the effectiveness of pre-rinse processing before the immersion exposure processing, and the material having the water repellency.
In the Proc. of SPIE, Vol. 7274, “Defectivity Improvement by Modified Wafer Edge Treatment in Immersion Lithography” (72741G, written by Fujita, 2009), there are considered the dependency by the bevel shape of a wafer, the elimination property of BARC in the edge rinse and the bevel rinse with various types of solvents, and the controllability of the cut surface.
As mentioned above, in the manufacturing process of a semiconductor device, especially in the manufacturing process of a semiconductor device using the liquid immersion lithography, the prevention of the dust generation in the wafer edge portions during the immersion exposure process is the most important problem in order to improve the manufacturing yield.
The applicants of the invention consider a method of manufacturing a semiconductor device that is superior in the elimination property of the organic films and the controllability on the cut surface, in order to restrain the dust generation in the wafer edge portions at the immersion exposure time using the BARC process and the C-HM process.
Other problems and novel features will be apparent from this specification and the attached drawings.